The present invention relates generally to semiconductor devices, and more particularly to bipolar semiconductor devices suitable as power switching elements.
Power MOSFETs have conventionally been used as power semiconductor devices having breakdown voltages of about 1,000 V or less.
Two types of these power MOSFETs have been widely known; one having a planar structure with a plate-shaped gate, and the other having a trench structure with a gate buried in a trench. It is generally thought that the trench structure is more advantageous than the planar structure in that the channel resistance can be easily reduced and the amount carriers to be injected in one chip can be easily increased.
FIG. 1 is a cross-sectional view showing a structure of a power MOSFET having this kind of trench structure. In this MOSFET, a low-concentration n- type base layer 2 and a p type base layer 3 are formed on a high-concentration n+ type drain layer 1. An n+ type source layer 4 is selectively formed on the p type base layer 3. A trench 5 is formed to extend from the n+ type source layer 4 through the p type base layer 3 into the n- type base layer 2. A gate electrode 7, surrounded by an insulating film 6, is formed in the trench 5.
On the other hand, a drain electrode 8 is formed on that surface of the n+ type drain layer 1, which is opposite to the surface thereof facing the n- type base layer 2. A source electrode 9 is formed on the n+ type source layer 4 and p type base layer 3 so as to be in contact with both layers 4 and 3.
The power MOSFET operates as follows.
When a positive voltage is applied to the drain electrode 8 and a negative voltage is applied to the source electrode 9, if a voltage which is positive relative to the source electrode is applied to the gate electrode 7, the conductivity of the surface of the p type base layer 3, which is in contact with the gate electrode 7, is inverted to the n-type, and electrons e are injected from the n+ type source layer into the n- type base layer 2 through the layer with inverted conductivity, and flow into the n+ type drain layer 1. Thus, the device is rendered conductive.
This power MOSFET is a so-called simple injection device using only the flow of current, and there is problem in that the resistance (on-resistance) in the turn-on state is high. The on-resistance results in a loss in the turn-on state of the device. The on-resistance is a very important characteristic which determines the conversion efficiency of a power electronics device, and therefore the on-resistance should be sufficiently low.
A description will now be given of an IGBT (Insulated Gate Bipolar Transistor) which can solve the above problem and is used as a power semiconductor device with a breakdown voltage of about 2,000 V or less.
FIG. 2 is a cross-sectional view showing the structure of the IGBT. In the IGBT, the n+ type drain layer 1 shown in FIG. 1 is replaced with a p+ type drain layer 10.
If a positive voltage is applied to the gate electrode 7, as with the above-described case, electrons e are injected into the n- type base layer 2 and reach the p+ type drain layer 10. As a result, holes h are injected from the p+ type drain layer 10 into the n- type base layer 2. Thus, both electrons e and holes h are injected in the n- type base layer 2, and a conductivity modulation occurs. Accordingly, the on-voltage can be reduced.
However, in the conductive state of the IGBT, the electrons e and holes h have to pass through a barrier of a built-in voltage provided between the n- type base layer 2 and p+ type drain layer 10. Consequently, the on-resistance, in particular, at the time of turn-on, cannot fully be reduced.
In brief, as shown in a current/voltage characteristic graph of FIG. 3, the power MOSFET has a problem in that the on-resistance is generally high as the inclination of on-current is gentle. The IGBT, on the other hand, has a problem in that the on-resistance is increased due to the built-in voltage of about 0.7 V at the time of turn-on.
In the field of modern power electronics technology, there is a demand for smaller sizes and higher performances of the power devices. Accordingly, power semiconductor devices have been required to have higher breakdown voltage, higher current, lower loss, and higher operation speed. In particular, in order to reduce the loss of the semiconductor device, it is necessary to reduce the above-mentioned on-voltage (constant loss) and turn-off loss. For this purpose, various device structures have been researched and developed.
Among others, there is known a semiconductor device with a feature of low on-voltage, which has a structure described, for example, in H. R. Chang et al., "MOS Trench Gate Field Controlled Thyristor", IEDM 89, pp. 293-296, 1989. This semiconductor device is an electrostatic induction thyristor having a buried insulated gate structure, for example, as shown in FIG. 4.
In FIG. 4, a high-concentration p+ type emitter layer 12 is formed on a surface of a high-resistance n- type base layer 11, and a plurality of striped trenches 13 are selectively are formed in the other surface of the base layer 11. An insulated gate electrode 15 is buried in each of the trenches 13, with a gate insulating film 14 interposed. An n+ type source layer 16 is formed on a surface of the n- type base layer 11 between the trenches 13 so as to be in contact with side surfaces of the trenches 13. A p type layer 17 is formed on a surface of the n- type base layer 11 in a peripheral region of an end of each trench 13 so as to be in contact with each trench and the n+ type source layer 16.
A drain electrode 18 is formed on that surface of the p+ type emitter layer 12, which is opposite to the surface thereof facing the n- type base layer 11.
A source electrode (not shown) is provided on the n+ type source layer 16 and p type layer 17 so as to be in contact with both layers 16 and 17.
FIG. 5 shows a potential distribution along line A-A' extending from the n+ type source layer 16 of this electrostatic induction thyristor through the center of an inter-trench region 19 to the drain electrode 18.
In the on-state of this semiconductor device, a zero potential, which is zero relative to the source, is applied to the insulated gate electrode 15. At this time, as shown in FIG. 5B, this semiconductor device operates as a p+nn+ diode, and the inter-trench region 19 functions as current path. Specifically, electrons e are injected from the n+ type source layer 16 via the inter-trench region 19 (n- region lying between the trenches) into the n- type base layer 11, and the holes h matching with the electrons e are injected from the p+ type emitter layer 12 into the n- type base layer 11. Thus, the n- type base layer 11 is filled with a great amount of accumulated carriers.
Thus, the semiconductor device is operable with a low on-voltage. This semiconductor device is of a normally-on type wherein the device is turned on when no voltage is applied to the insulated gate electrode 15.
On the other hand, in a turn-off operation, a negative voltage, which is negative relative to the source, is applied to the insulated gate electrode 15. Thereby, a depletion layer is formed in the inter-trench region 19 near the side surfaces of the trenches 13 and, as shown in FIG. 5A, a potential barrier against the electrons e is formed by pinching-off and the injection of electrons is stopped. Besides, part of the holes h in the n- type base layer 11 is discharged to the source electrode via the p type layer 17, and the other part of holes h is recombined with the electrons e and extinguished. Thus, the semiconductor device is turned off.
Even in this type of semiconductor device, however, there is a problem in that the on-voltage cannot be decreased to a built-in voltage VB or less. The reason is that a pn junction is formed by the p+ type emitter layer 12 and n- type base layer 11 and the built-in voltage VB of the pn junction is included in the on-voltage.noteq.(VN+VB) of the device. The symbol VN denotes a voltage drop in the n- type base layer 11.
This semiconductor device has another problem in that the turn-off performance is low. This problem arises due to the absence of a mechanism for positively discharging the great amount of accumulated carriers in the n- type base layer 11 at the time of turn-off. In particular, if discharge of holes h is delayed, no depletion layer is formed in the inter-trench region 19. Consequently, injection of electrons e from the n+ type source layer 16 does not stop, and injection of holes h from the p+ type emitter layer 12 is continued. Thus, the semiconductor device cannot be turned off.
The above description relates to the power semiconductor device having the trench structure. Next, a description will be given of a planar-structure power transistor which is a typical medium capacity device most widely used at present in various fields.
FIG. 6 is a cross-sectional view showing the structure of an npn power transistor. In this power transistor, a high-concentration n- type collector layer 1a is formed on a surface of a high-resistance n type base layer 2a. A p type base layer 3a is formed on the other surface of the n- type base layer 2a. An n+ type emitter layer 4a is selectively formed on a surface of the p type base layer 3a. A base electrode 7a is formed on that region of the surface of the p type base layer 3a, which differs from the region where the n+ type emitter layer 4a is formed. A collector electrode 8a is provided on the n+ type collector layer 1a, and an emitter electrode 9a is provided on the n+ type emitter layer 4a.
This power transistor operates as follows.
Suppose a positive potential is applied to the collector electrode 8a and a zero voltage is applied to the emitter electrode 9a. At the time of turn-on, the base electrode 7a is supplied with a positive potential which is higher than a built-in voltage of a pn junction formed by the p type base layer 3a and n+ type emitter layer 4a.
Thus, as shown in FIG. 7, holes are injected into the n+ type emitter layer 4a from the base electrode 7a through the p type base layer 3a, and electrons e are injected from the n+ type emitter layer 4a into the p type base layer 3a. Part of the electrons e is recombined with the holes h in the p type base layer 3a and extinguished. However, since the p type base layer 3a is very thin and the collector electrode 8a is biased to a positive potential, most of the electrons e is injected from the p type base layer 3a into the n- type base layer 2a and then flows to the collector electrode 8a through the n+ type collector layer 1a. If the electrons e are injected in the n- type base layer 2a, the holes h are injected in the n- type base layer 2a as well, so as to meet the condition of charge neutralization. Thereby, conductivity modulation occurs and the power transistor is rendered conductive.
On the other hand, at the time of turn-off, the base electrode 7a is supplied with a negative potential which is lower than a breakdown voltage of the pn junction formed by the p type base layer 3a and n+ type emitter layer 4a. Thereby, the base/emitter path is reversely biased, and injection of electrons from the n+ type emitter layer 4a is stopped. In addition, the holes h accumulated in the n- type base layer 2a are discharged from the base electrode 7a, and the device is turned off.
This power transistor is characterized in that the holes h are injected from the p type base layer 3a into the n- type base layer 2a and thus the conductivity modulation occurs in the n- type base layer 2a, whereby the on-voltage can be reduced and a large current can be controlled.
However, in the conventional power transistor, most of the hole current injected from the base electrode 7a in the turn-on state does not flow to the n- type base layer 2a but flows directly to the n+ type emitter layer 4a through the p type base layer 3a. Consequently, a large base current is required and a current gain (DC amplification factor: h.sub.FE =IC/IB) is low.
Moreover, at the time of turn-off, a negative voltage exceeding a base/emitter breakdown voltage cannot be applied to the base electrode 7a. Thus, the turn-off performance is low.
In the meantime, in the case where the above-described power semiconductor device is applied to a switching circuit for an inverter circuit or a chopper circuit, a demand for a smaller size and a higher performance of the power semiconductor device has increased more and more.
In the case of the inverter circuit, a load has an inductance component like a motor control. When the power transistor serving as a switching element is turned off, energy accumulated in the inductance of the load needs to be discharged. In order to circulate this electric energy, the inverter circuit, as shown in FIG. 8, comprises circulation diodes (freewheel diodes) D1 to D4 which are connected in reverse-parallel to power transistors T1 to T4. Base signals I.sub.B1 to I.sub.B4 are applied to the bases of power transistors T1 to T4 by driver circuits (not shown).
For example, if base signals I.sub.B1 to I.sub.B4 are applied to the power transistors T1 to T4, as shown in FIG. 9, an output voltage V.sub.inv is applied to a load. Specifically, a dead time for switching is considered, and the base signals I.sub.B1 to I.sub.B2 are not simultaneously turned on/off, as shown in FIG. 10. The output voltage V.sub.inv corresponds to the base signal I.sub.B1, and a freewheel current I.sub.D1 of the freewheel diode D1 is inverse to the base signal I.sub.B1. The actual output voltage V.sub.inv corresponds to the base signal subjected to pulse width modulation (PWM), as shown in the waveform of FIG. 11.
In this inverter circuit, a breakdown voltage higher than the power supply voltage is achieved by the power transistors T1 to T4 and freewheel diodes Dl to D4. Thus, a junction end region of a predetermined area or more is required in the semiconductor chip.
Accordingly, reduction in chip area is difficult, and high current density cannot be achieved.
When this inverter circuit is constructed as modules, the freewheel diodes D1 to D4 are externally connected to the power transistors T1 to T4. The power transistor chip and the freewheel chip are mounted on a single substrate, and electrodes on the chips are connected to external led-out electrodes by means of wiring. Owing to an inductance of connection wiring, a high-speed operation is difficult.
As has been described above, the conventional semiconductor device has the problems in that the on-voltage cannot be lowered to the built-in voltage or less, and the turn-off performance is low.
Furthermore, there are the problem of low current gain and the problem of low turn-off performance.
Besides, there is the problem in that the freewheel diodes D1 to D4 are connected in inverse-parallel to the power transistors T1 to T4 and consequently high current density cannot be achieved and high-speed operation cannot be performed due to inductance in the connection wiring.